Metallization structures constitute an integral part of many electronic devices and components. Some metallization structures serve as wiring that electrically interconnects active devices, such as transistors, while some other metallization structures serve as passive or active devices themselves, such as inductors, resistors or transformers. Some metallization structures can be formed as an integral part of an integrated circuit (IC) device, while other metallization structures can be formed as part of a package that houses the IC device and connects the IC device to the outside world.
Depending on the material of the conductors and the material of the dielectric surrounding the conductors, the metallization structures can be formed using various processes. For example, for interconnecting IC chips, metallization structures can be formed using printed circuit board (PCB) technology, co-fired ceramic technology or thin film integration technology, to name a few. Some thin film integration technologies integrate metal film structures with organic interlayer dielectric layers on rigid inorganic substrates such as silicon or aluminum nitride. Some thin film integration technologies can allow for integration of metallization structures at relatively higher density and higher performance compared to PCB and co-fired ceramic technology.
The thin film integration technology can in turn form the metallization structures using various methods, including subtractive etch, metal stencil lift-off, plating, and damascene methods, to name a few. In a subtractive etch process, a blanket film of metal, e.g., aluminum or gold, is deposited by sputtering or evaporation and subsequently photo-patterned with resist, followed by an etch process to form the metallization structures. In a metal stencil lift-off process, a pattern is first defined by photoresist, followed by a blanket deposition of metal layer(s) using evaporation or sputtering over the entire substrate. After the blanket metal deposition, the resist is lifted-off, leaving the metallization structures on the substrate. In some plating processes, a blanket deposition of a barrier layer and/or an adhesion when one or both are present and a seed layer is followed by photopatterning a masking layer or a patterning layer, e.g., photoresist or a photosensitive polyimide layer, to define areas in which a metal is subsequently electroplated. In a damascene process, conducting features are formed by first defining openings (e.g., trenches, vias) in a dielectric material, followed by backfilling the openings with a metal, then removing the excess metal by a planarization step. The adhesion, barrier and/or seed layer(s) may be under or over the dielectric material.
Challenges associated with integrating the thin-film materials and structures in forming the metallization structures by plating include forming metallization structures having relatively large thicknesses while ensuring high integrity and reliability of the final product and maintaining economic feasibility. Various structures and methods according to embodiments disclosed herein addresses these and other challenges associated with forming the metallization structures by plating, e.g., electroplating.